1. Field of the Invention
The present invention, generally, relates to data processing computer systems and, more particularly, to a new and improved system of arbitration for access to a random access memory unit by a plurality of asynchronous microprocessor devices.
It is common practice in networks having multiple microprocessors that two of the microprocessors will share large amounts of memory. It is known also that, as between two such microprocessors, a system of arbitration must be provided to control their access to the common memory. The problem is compounded when the microprocessors are asynchronous.
There are many off-the-shelf vendor components available today that have Dual Port Memory Controls which include various amounts of memory with each module, but a difficulty is experienced in attempting to use them with microprocessors that are asynchronous. Another difficulty with such components available today is that the memory associated with these components are too small or that the memory controls do not match the control needs as between two microprocessors because of a mismatch with the synchronism of the microprocessors.
In the past, it has been customary in a device utilizing a plurality of microprocessors for one microprocessor to be connected to a memory unit to the exclusion of the others. Other microprocessors may obtain access only while the memory unit is "idle".
It was recognized early in the art that if the common memory unit could be utilized more efficiently, the efficiency of the whole computer network would be improved. Thereafter, the search was on to develop a wide variety of systems, techniques and/or devices to permit such improvement.
2. Description of the Prior Art
From about the mid 1970's to about the mid 1980's, the search for an improvement in the overall efficiency of utilization of a common memory as between at least two memory utilization devices was most intense. However, many arrangements developed during this period used a system involving a "wait" signal to identify the microprocessor that was to be denied access to the common memory.
The microprocessors that are arranged to use the "wait" signal (in contrast with a "not ready" signal) stop functioning at cycle boundaries. Then, such microprocessors release their control lines to other devices.
An early to Matsumoto U.S. Pat. No. 4,065,809 was issued in 1977 and involves two synchronous CPU's with a simple flip-flop to render one CPU inactive when the other CPU is active. While effective in a simple arithmetic environment, this arrangement is inoperative in a complex environment in which the present invention is adapted to function.
U.S. Pat. No. 4,096,572 issued in June, 1978, to Namimoto and teaches the use of a handshake system with a "wait" signal, if there is a memory access conflict. A request for access to the common memory is responded to by an "acknowledge" or a "wait" signal, and processors provide memory access timing. The present invention does not use a request/acknowledgement handshake method, as will be understood better as the description proceeds.
In October, 1978, U.S. Pat. No. 4,121,285 issued to Chen. This patent teaches that, when several devices must access a common unit, equal priority is provided. This arrangement only determines priority and does not provide for any access timing, as with the present invention.
Then, in December, 1978, U.S. Pat. No. 4,128,881 issued to Yamamoto et al. The arrangement taught by this patent provides a different, pre-fixed address for each processor that must have access to a common memory. This arrangement does not involve a need to determine priority between the processors and, therefore, is completely at variance with the present invention.
A more recent U.S. Pat. No. 4,542,454 issued September, 1985, to Brcich et al. is entitled "Apparatus For Controlling Access To A Memory". However, its system is for access to a memory by a single processor for different purposes. It teaches using a dynamic memory controller 26 to obtain access under four different modes or functions, such as (1) refresh without error detection, (2) refresh with error detection, (3) clear and (4) read/write.
Therefore, the need still exists today for a control to arbitrate effectively between two asynchronous microprocessors in a network having a common memory. The present invention not only provides such an arbitration control device but reduces the usual cost of these devices while, in addition, providing other desirable and useful features, as will become more readily apparent.